Thermal-aware 3D Multi-core Processor Design using Core and Level-2 Cache Placement

As integration densities continue to increase, interconnection has become one of the most important factors in determining the performance of multi-core processors. Recently, in order to reduce the delay due to interconnection, many studies have focused on the 3D multi-core processors. Compared to 2D multi-core architecture, 3D multi-core architecture gets decreased interconnection delay and lower power consumption owing to reduced wire length. Despite the benefits mentioned above, 3D design cannot be practical because it causes serious thermal problems in multi-core processors due to high power density. In this paper, we analyze temperature behavior of 3D multi-core processors according to various placement of core and level-2 cache. According to our simulation results, the floorplan where the core is stacked adjacently to the level-2 cache can reduce the temperature by 22% with 4layers, and by 13% with 2-layers on the average, compared to the floorplan where the core is stacked adjacently to the core.